condition codes

The rest of the word is single bit condition codes.

Arithmetic and logic instructions also set the condition codes.

Delivery condition codes are also relatively common, the most common being:

Another 2009 California study found that the reported increases are unlikely to be explained by changes in how qualifying condition codes for autism were recorded.

It provides dual integer condition codes to allow 32-bit and 64-bit code to co-exist.

The 8 bit EC register contains condition codes bits.

Some additional extended jump condition codes allow debug functions, such as interrupt, stop and pause.

Arithmetic instructions alter condition codes only when desired.

There are 8 variants of the instruction selected by the condition codes that need be set for the instruction to perform the move.

Most other CPU architectures only have condition codes on branch instructions.

The Alpha does not have condition codes for integer instructions to remove a potential bottleneck at the condition status register.

A call's state at any given time is denoted by one of several different "condition codes," each is expressed visually by a different color.

In the optimization phase, the operating condition constraints, optimal solution, and linear programming health status condition codes were recorded.

Most Branch instructions take conditional effect based on the state of the condition codes in the PSW.

SCC and CCC respectively set and clear all four condition codes.

Bit test operations have also been added, performing a logical AND function between operands, setting the correct conditions codes, but not modifying the operands.

In many designs, the ALU also takes or generates inputs or outputs a set of condition codes from or to a status register.

Prefix codes are also known as prefix-free codes, prefix condition codes and instantaneous codes.

It also saves the frame pointer, loads integer regstier zero with the value 3, and increments integer register 31 without changing the condition codes.

The jump condition codes have been extended to cope with the new overflow flag, and now include all the conditions available on general purpose micro-processors, e.g. the 68000.

These instructions save or restore the condition codes containing USER or IOT bits:

Update the "condition codes" with the ALU status flags ("Negative", "Zero", "Overflow", and "Carry")

A classic example of a hidden side effect is an arithmetic instruction which explicitly modifies a register (an overt effect) and implicitly modifies condition codes (a hidden side effect).

For other conditional branches, the first two production models implemented predict untaken; subsequent models were changed to implement predictions based on the current values of the indicator bits (corresponding to today's condition codes).

MOVE from SR This instruction is sensitive because it allows access to the entire status register, which includes not only the condition codes but also the user/supervisor bit, interrupt level, and trace control.