condition code register

Another difference, this one not so odd, is that the 29000 included no special-purpose condition code register.

For example, the condition code register might not directly writable, instead being updated only by compare instructions.

It should also be noted that condition code register (CCR) affects the decryption process.

The BPU contains the program counter, the condition code register and a loop register.

The condition code register has eight field sets, with the first two reserved for fixed and floating point instructions and the seventh for vector instructions.

A status register or flag register (also: condition code register, program status word, PSW, etc.) is a collection of flag bits for a processor.

It has two eight-bit accumulators, A and B, two sixteen-bit index registers, X and Y, a condition code register, a 16-bit stack pointer, and a program counter.

It had thirty-one 32-bit general purpose registers, but no condition code register (the designers considered it a potential bottleneck), a feature it shares with the AMD 29000 and the Alpha.

In most later family members, starting with the MC68010, the MOVE from SR instruction was made privileged, and a new MOVE from CCR instruction was provided to allow access to the condition code register only.

Thirteen registers were in the Command Computer, mostly obvious types such as an 18-bit accumulator, 12-bit program counter, 12-bit link register that pointed to the next address to be read, and a 4-bit condition code register that stored the overflow, minus, odd parity, and nonzero flags77.