Conditional branch instructions test the various flag status bits.

You're chugging along, then you hit a branch instruction and jump to some subroutine.

A more sophisticated design would execute program instructions which are not dependent on the result of the branch instruction.

Instead it predicts the outcome of a branch based solely on the branch instruction.

The opcode used indicated the history of that particular branch instruction.

It is an abbreviated instruction trace in which only the successful branch instructions are recorded.

Instructions that decide what the next instruction should be are called branch instructions.

Furthermore, slot 4 can hold only branch instructions and nothing else.

However, it has a higher latency than conditional branch instructions.

Relative branch instructions supply an 8-bit signed offset which is added to the PC.